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Seminario del Dr. Federico Angiolini

Del 13 al 17 de mayo nos visitará el profesor Federico Angiolini, el cual impartirá un curso en el ámbito de la asignatura Redes en Chip

Course title:

Network-on-Chip design for Systems-on-Chip

Course description:

In recent years, chip integration has become so extreme that numerous large functional units, or "IP cores", can be placed on a single silicon die, giving birth to so-called "Systems-on-Chip" (SoCs). With the cheap availability of such computation power, the challenge is now about providing sufficient on-chip communication resources so that the many IP cores can effectively exchange inputs and outputs, and access on-chip and off-chip memory. The academia and industry both agree that the solution is to borrow concepts from decades of research in large communication networks, such as packet-switched communication, giving birth to "Networks-on-Chip" (NoCs). NoCs are becoming the backbone of modern SoCs, and are thus appearing in such cutting-edge and diverse systems as automotive electronics, smartphone chips, set-top boxes, etc.


  • Monday 13 May, 18:15-20:45: "Network-on-Chip Synthesis".

The basic concepts of NoC design, and why design automation can be helpful. The iNoCs NoC synthesis algorithms. Communication use cases, the benefits and challenges of having multiple voltage and frequency islands, power management, and strategies to handle constraints and degrees of freedom. Topology ranking and comparison.


  • Tuesday 14 May, 15:30-18:00: "NoC Physical Design".

Physical-level metrics that are important for NoC synthesis (frequency, area, power). Characterization flows of the above. Link length constraints, motivating the importance of accounting for floorplanning during NoC design. The iNoCs integrated floorplanning features.


  • Wednesday 15 May, 15:30-18:00: "NoC Architecture, RTL, and Simulation".

Brief overview of the iNoCs IP library. Network Interfaces at the heart of NoC RTL complexity; IP core protocol features, system interoperability strategies, packetization tradeoffs. Challenges in interface modeling. Simulation as a tool for performance verification.


  • Friday 17 May, 15:30-18.00: "Future NoC Avenues".

NoC design for fault tolerance. Service and QoS provisioning in NoCs. The evolution of SoC platforms: subsystems and interconnect. NoCs applied to (near-)future manufacturing technologies: 3D-stacked NoCs, wireless NoCs, optical NoCs.

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